FPGA design acceleration – idiomatic Python to synthesizable Verilog

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FPGA design acceleration – idiomatic Python to synthesizable Verilog

Recently I've been working on a certain embedded system that has an FPGA running EKF and some controls. Coding that in RTL is inefficient at best so I turned to HLS and looked around to see what the industry has to offer. I have a pretty extensive simulation and verification scaffold in Python, so ideally I wanted something that can accept Python directly, preferably with minimal adaptation, so that I could feed relevant parts of my Python models to the HLS tool and immediately get a working RTL out. Also I wanted floating point. I should add that my FPGA here is Lattice ECP5 which means that Vitis et al are not an option, so I was focusing on vendor-agnostic tools. There are some that can ingest Python but they are frankly not really usable in practice aside from perhaps a very narrow set of applications -- I evaluated Polyphony, PyLog, Allo+XLS, Allo+Vitis (not really an option because Lattice), and Veriloggen. They work in the sense that they translate some Python into some RTL, but not in the sense that you can get something immediately useful out of them if you're trying to build, say, a Kalman filter or even a basic PID controller. Then there are highly capable tools like the aforementioned XLS, Bambu, etc. that unfortunately don't support Python and there are a few shortcomings (especially when it comes to ECP5) that I will cover someday in a later post. So, behold Holoso: https://github.com/Zubax/holoso To me personally this is a big deal because it has already enabled dramatic acceleration of my work. The feature set is currently mostly defined by my immediate needs but it is extensible and contributions are welcome. I will spare a detailed explanation of how it works (follow the link for that) but the basic idea is that it parses Python, constructs a CFG, identifies which operators are needed, constructs a minimal specialized VLIW core, schedules microcode (fully statically to keep the core simple), and emits Verilog along with some extra outputs like Cocotb and reports. There are examples included that will give you a better feel of what it's like; there are even some exotic ones like UART rx/tx, which I would not call a sensible use of this tool but it's mostly there to outline its limits more clearly -- it's an HLS, not an RTL, so keep that in mind. I have already benchmarked it side by side with Bambu, XLS, Dynamatic, and Vitis, and the results seem decent; I am going to post about this later if there's interest (still working on this). Holoso is available under Apache-2 with explicit legal waivers for generated RTL. Hopefully someone will find it useful as well!